Semiconductor device and its manufacturing method

ABSTRACT

A semiconductor device in which a semiconductor chip ( 3 ) is mounted on a substrate ( 2 ), comprising a substrate having electrodes ( 7, 8 ) for substrate-to-substrate connection disposed on both sides of the substrate and connected via a through hole ( 9 ), a semiconductor chip having an electrode connected to a wiring pattern arranged on the substrate and having a flat-cut face opposite to the face where the electrode is provided, a bump ( 4 ) for substrate-to-substrate connection provided on the electrode for substrate-to-substrate connection and having a flat-cut face opposite to the face facing the substrate, a sealing resin body ( 5 ) provided on the substrate, used for sealing the semiconductor chip and the bump for substrate-to-substrate, and having a flat-cut face opposite to the face facing the substrate, wherein the flat-cut face ( 3   a ) of the semiconductor chip, the flat-cut face ( 4   a ) of the bump for substrate-to-substrate, and the flat-cut face ( 5   a ) or the sealing resin body are flush with one another, and the semiconductor chip and the bump for disk recording medium except for the flat-cut faces are scaled in the sealing body.

TECHNICAL FIELD

The present invention relates to a semiconductor device and a method formanufacturing it, and more particularly to a layered semiconductordevice and a method for manufacturing it.

BACKGROUND ART

In recent electronic devices, arrangements to realize compact forms andhigher functions of them have been made. In order to make the electronicdevices compact and obtain the higher functions of them, it has beendemanded to mount semiconductor devices of large capacity with smallmounting areas and small mounting volume as much as possible.

For instance, in the electronic device using a semiconductor memory, anattempt has been made to make the device more compact with the increaseof an amount of treated information. As the amount of informationhandled by the electronic device increases, it has been also demandednot only to increase the capacity of the semiconductor memory used forstoring the information, but also to make the semiconductor memorymounted in the electronic device compact so as to meet the compactelectronic device. In other words, the mounting area and the mountingvolume of the semiconductor memory to be mounted in the electronicdevice have been desired to be decreased.

Thus, there has been proposed various kinds of semiconductor devices inwhich a plurality of semiconductor memories are combined to increase thestorage capacity. FIGS. 1 to 3 show one example of such semiconductordevices.

In the semiconductor device shown in FIGS. 1 to 3, a semiconductor chip101 forming a semiconductor memory is firstly prepared. The back surfaceof the semiconductor chip 101, that is, a surface 102 opposite to asurface on which a connecting terminal to a substrate is formed isground to form a mounting semiconductor chip 103 whose thickness isreduced. The semiconductor chip 103 which is ground is reversed, thatis, the semiconductor chip 103 is mounted on a substrate 104 with theground surface used as a mounting surface, as shown in FIG. 1. On boththe front and back surfaces of the substrate 104, are formedinter-substrate connecting electrodes 105 and 106 electrically connectedto a wiring pattern to which the semiconductor chip 103 mounted on thesubstrate 104 is electrically connected. These inter-substrateconnecting electrodes 105 and 106 are electrically connected to eachother through through holes 107 opened on the substrate 104. On theinter-substrate connecting electrodes 105 formed on the surface on whichthe semiconductor chip 103 is mounted, solder bumps 108 with prescribedheight are formed to form a semiconductor device 109 as shown in FIG. 2.

A plurality of the semiconductor devices 109 formed as shown in FIG. 2are stacked so as to be layered and the solder bumps 108 arerespectively connected to the inter-substrate connecting electrodes 106so that a layered semiconductor device 110 as shown in FIG. 3 is formed.

As described above, the semiconductor chip 101 is ground to decrease thethickness so that the thickness of the layered semiconductor device 110obtained by layering these semiconductor chips 101 in multiple stagescan be reduced. The thickness of the layered semiconductor device 110formed by layering a plurality of the above-described semiconductordevices 109 can be adequately reduced.

In the semiconductor device 109 used for the above-described layeredsemiconductor device 110, since the semiconductor chip 101 as a simplesubstance is ground to obtain the mounting semiconductor chip 103 whosethickness is reduced, a load exerted on the semiconductor chip 101 islarge. Thus, there arises a great risk that cracks or the like may bepossibly formed on the semiconductor chip 101 and the semiconductor chip101 may be broken. Therefore, there is a limit to reduce the thicknessof the semiconductor chip 101 and the thickness of the semiconductorchip is hardly reduced to a desire thickness.

In order to lighten the load exerted on the semiconductor chip 101 upongrinding, there may be considered a method that after the semiconductorchip 101 is mounted on the substrate, all the peripheral surface of thesemiconductor chip 101 is completely covered with a synthetic resin forencapsulating, and then, the semiconductor chip 101 is ground togetherwith the encapsulating resin. In such a manner, since the load exertedon the semiconductor chip upon grinding is distributed to theencapsulating resin, even when the semiconductor chip 101 is grounduntil its thickness is adequately decreases, the damage of thesemiconductor chip 101 such as cracks can be avoided.

When all the surface of the outer periphery of the semiconductor chip101 mounted on the substrate is covered with the encapsulating resin,the inter-substrate connecting electrodes 105 and 106 are also coveredwith the encapsulating resin. Accordingly, in order to layer the pluralsemiconductor chips 101, it is necessary to remove the encapsulatingresin with which the inter-substrate connecting electrodes are coveredby using a laser beam or the like, or form in the encapsulating resinholes reaching the inter-substrate connecting electrodes and fill theholes with soft solder. The holes have bottoms, and it is very difficultto fill the holes having the bottoms with the soft solder so as not tosupply air bubbles to the holes. For instance, it is extremely difficultto supply the soft solder by a simple screen printing method.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a new semiconductordevice capable of overcoming the above-described problems of theconventional semiconductor device, a layered semiconductor device usingthis semiconductor device and a method for manufacturing thesesemiconductor devices.

It is another object of the present invention to provide a semiconductordevice which realizes a thinner device and can increase a capacity whilerealizing the thinner device, a layered semiconductor device using thissemiconductor device and a method for manufacturing these semiconductordevices.

In order to overcome the above-described problems, a semiconductordevice according to the present invention comprises: a substrate havinginter-substrate connecting electrodes formed on both front and backsurfaces and connected by through holes; a semiconductor chip havingelectrodes connected to a wiring pattern formed on the substrate and asurface opposite to an electrode forming surface cut flat;inter-substrate connecting bumps provided on the inter-substrateconnecting electrodes on the substrate and having surfaces opposite tothe substrate cut flat; and an encapsulating resin provided on thesubstrate to encapsulate the semiconductor chip and the inter-substrateconnecting bumps and having surfaces opposite to the substrate cut flat,wherein the cut flat surface of the semiconductor chip, the cut flatsurfaces of the inter-substrate connecting bumps and the cut flatsurfaces of the encapsulating resin are located in the same plane andthe semiconductor chip and the inter-substrate connecting bumps areencapsulated in the encapsulating resin except the cut flat surfaces.

In the semiconductor device according to the present invention proposedfor achieving the above-described objects, since the semiconductor chipis cut together with the encapsulating resin to have a desiredthickness, a load upon cutting is distributed to the encapsulatingresin, and accordingly, the damage of the semiconductor chip such ascracks can be reduced and the semiconductor chip can be cut more to bethinner.

Further, since the inter-substrate connecting bumps are formed on theinter-substrate connecting electrodes, covered with the encapsulatingresin and then cut together with the encapsulating resin to be exposed,there is no fear that the connection between the inter-substrateconnecting bumps and the inter-substrate connecting electrodes may bepossibly imperfect, and the connecting end faces of prescribed areas areformed.

In a layered semiconductor device according to the present inventionhaving a plurality of semiconductor devices, each semiconductor devicecomprises: a substrate having inter-substrate connecting electrodesformed on both front and back surfaces and connected by through holes; asemiconductor chip having electrodes connected to a wiring pattern onthe substrate on the front surface or both the front and back surfacesof the substrate and a surface opposite to an electrode forming surfaceon which the electrodes are formed cut flat; inter-substrate connectingbumps provided on the inter-substrate connecting electrodes on the frontsurface or both the front and back surfaces of the substrate and havingsurfaces opposite to the substrate cut flat; and an encapsulating resinprovided on the front surface or both the front and back surfaces of thesubstrate to encapsulate the semiconductor chip and the inter-substrateconnecting bumps and having surfaces opposite to the substrate cut flat.In the layered semiconductor device, are layered a plurality ofsemiconductor devices each of which has the cut flat surface of thesemiconductor chip, the cut flat surfaces of the inter-substrateconnecting bumps and the cut flat surfaces of the encapsulating resinlocated in the same plane and the semiconductor chip and theinter-substrate connecting bumps encapsulated in the encapsulating resinexcept the cut flat surfaces. The inter-substrate connecting bumps ofthe respective semiconductor devices are connected together or theinter-substrate connecting bumps are connected to the inter-substrateconnecting electrodes.

In the layered semiconductor device according to the present invention,since a plurality of semiconductor devices having the semiconductorchips cut to be extremely thin can be layered, a compact and especiallythin layered semiconductor device with more improved integration can berealized.

A method for manufacturing a semiconductor device according to thepresent invention comprises the steps of forming inter-substrateconnecting bumps on one of a front surface or both of front and backsurfaces of inter-substrate connecting electrodes formed on both thefront and back surfaces of a substrate, connected by through holes andconnected to a wiring pattern so as to be higher than required height;connecting electrodes of a semiconductor chip to the wiring patternformed on the substrate and mounting the electrodes of the semiconductorchip on the front surface or both the front and back surfaces of thesubstrate; applying an encapsulating resin to the substrate so as tocover the semiconductor chip and the inter-substrate connecting bumpstherewith; and cutting flat the surfaces of the encapsulating resin, thesemiconductor chip and the inter-substrate connecting bumps opposite tothe substrate so that the space between the cut flat surfaces of theencapsulating resin, the semiconductor chip and the inter-substrateconnecting bumps and the substrate has a prescribed thickness.

In the method for manufacturing a semiconductor device according to thepresent invention, since the semiconductor chip is cut together with theencapsulating resin, stress exerted on the semiconductor chip uponcutting is decreased so that the damage of the semiconductor chip suchas cracks is reduced and the semiconductor chip can be cut to bethinner.

Since the inter-substrate connecting bumps are previously applied to theinter-substrate connecting electrodes, then encapsulated by theencapsulating resin and the connecting end faces are exposed by cutting,the connected states of the inter-substrate connecting bumps and theinter-substrate connecting electrodes are not unstable and theconnecting end faces of prescribed areas can be ensured. Thus, theconnection between the respective semiconductor devices when a pluralityof semiconductor devices are layered can be easily carried out.

Further, the inter-substrate connecting bump are applied to theinter-substrate connecting electrodes before the semiconductor chip ismounted on the substrate, so that there is no fear that a connectingmaterial for connecting the semiconductor chip to the wiring pattern onthe substrate may possibly flow out to the inter-substrate connectingelectrodes to prevent the connection between the inter-substrateconnecting electrodes and the inter-substrate connecting bumps or theconnection between the substrates, and the inter-substrate connectingelectrodes can be provided in positions near areas where thesemiconductor chips are mounted and the compact semiconductor device,especially, a compact planar configuration can be realized.

A method for manufacturing a layered semiconductor device according tothe present invention comprises the steps of: forming inter-substrateconnecting bumps on one of a front surface or both of front and backsurfaces of inter-substrate connecting electrodes formed on both thefront and back surfaces of a substrate, connected by through holes andconnected to a wiring pattern so as to be higher than required height;connecting electrodes of a semiconductor chip to the wiring patternformed on the substrate and mounting the electrodes of the semiconductorchip on the front surface or both the front and back surfaces of thesubstrate; applying an encapsulating resin to the substrate so as tocover the semiconductor chip and the inter-substrate connecting bumpstherewith; and cutting flat the surfaces of the encapsulating resin, thesemiconductor chip and the inter-substrate connecting bumps opposite tothe substrate to have the space of a prescribed thickness between thecut flat surfaces of the encapsulating resin, the semiconductor chip andthe inter-substrate connecting bumps and the substrate so that eachsemiconductor device is formed; layering a plurality of semiconductordevices thus formed; and then, connecting the inter-substrate connectingbumps of the respective semiconductor devices together or theinter-substrate connecting bumps to the inter-substrate connectingelectrodes.

In the method for manufacturing the layered semiconductor device, aplurality of semiconductor devices each of which has a semiconductorchip cut extremely thin can be layered so that a compact and, especiallythin layered semiconductor device with high integration can bemanufactured and the respective semiconductor devices can be connectedtogether with high accuracy.

Another semiconductor device according to the present inventioncomprises a substrate having inter-substrate connecting electrodesformed on both front and back surfaces and connected by through holes; asemiconductor chip having electrodes connected to a wiring patternformed on the substrate and a surface opposite to an electrode formingsurface cut flat; inter-substrate connecting bumps provided on theinter-substrate connecting electrodes on the substrate and havingsurfaces opposite to the substrate cut flat after they are previouslymade to collapse to prescribed thickness; and a polymer material locatedso as to surround parts between the substrate and the semiconductor chipand the side surfaces of the semiconductor chip to secure thesemiconductor chip to the substrate, and the cut flat surface of thesemiconductor chip and the cut flat surfaces of the inter-substrateconnecting bumps are located in the same plane. Since the semiconductordevice is secured to the substrate by the polymer material located so asto surround the parts between the semiconductor chip and the substrateand the side surfaces of the semiconductor chip, load upon cutting isdistributed to the polymer material and the substrate to decrease thedamage of the semiconductor such as cracks, and accordingly, thesemiconductor chip can be cut thinner.

Since the inter-substrate connecting bumps are made to collapse toprescribed thickness after they are formed on the inter-substrateconnecting electrodes, and then, cut together with the semiconductorchip, there is no possibility that the connection between theinter-substrate connecting bumps and the inter-substrate connectingelectrodes may be imperfect and the connecting end faces of prescribedareas are formed. Further, the inter-substrate connecting bumps are madeto collapse so that the inter-substrate connecting bumps effectivelycome into contact the inter-substrate connecting electrodes and thesubstrate, and the inter-substrate connecting bumps may not possiblyslip out of the substrate due to a cutting operation. Further, theinter-substrate connecting bumps are previously made to collapse to havea thickness near a final thickness, so that the cutting operation iseasily carried out.

Another layered semiconductor device having a plurality of semiconductordevices according to the present invention, each semiconductor devicecomprises: a substrate having inter-substrate connecting electrodesformed on both front and back surfaces and connected by through holes; asemiconductor chip having electrodes connected to a wiring patternformed on the substrate on the front surface or both the front and backsurfaces of the substrate and a surface opposite to an electrode formingsurface cut flat; inter-substrate connecting bumps provided on theinter-substrate connecting electrodes on the substrate and havingsurfaces opposite to the substrate cut flat after they are previouslymade to collapse to a prescribed thickness; and a polymer materiallocated so as to surround parts between the substrate and thesemiconductor chip and the side surfaces of the semiconductor chip tosecure the semiconductor chip to the substrate, the cut flat surface ofthe semiconductor chip and the cut flat surfaces of the inter-substrateconnecting bumps being located in the same plane to obtain eachsemiconductor device, and further layering the plural semiconductordevices thus formed, and the inter-substrate connecting bumps of therespective semiconductor devices are connected together or theinter-substrate connecting bumps are connected to the inter-substrateconnecting electrodes. According to the present invention, a pluralityof semiconductor devices each of which has the thin cut semiconductorchip can be layered, and accordingly, a compact and especially thinlayered semiconductor device with high integration can be obtained.

Another method for manufacturing a semiconductor device according to thepresent invention comprises the steps of forming inter-substrateconnecting bumps on one of a front surface or both of front and backsurfaces of inter-substrate connecting electrodes formed on both thefront and back surfaces of a substrate, connected by through holes andconnected to a wiring pattern so as to be higher than required heightand making the inter-substrate connecting bumps to collapse in thedirection of the thickness of the substrate to have the height near therequired height; connecting electrodes of a semiconductor chip to thewiring pattern formed on the substrate and mounting the electrodes ofthe semiconductor chip on the front surface or both the front and backsurfaces of the substrate and securing the semiconductor chip to thesubstrate by a polymer material located so as to surround parts betweenthe substrate and the semiconductor chip and the side surfaces of thesemiconductor chip; and cutting flat the surfaces of the semiconductorchip and the inter-substrate connecting bumps opposite to the substrateto have the space of a prescribed thickness between the cut flatsurfaces of the semiconductor chip and the inter-substrate connectingbumps and the substrate. According to the present invention, since thesemiconductor chip is cut while the semiconductor chip is secured to thesubstrate by the polymer material, stress exerted on the semiconductorchip upon cutting is decreased so that the damage of the semiconductorchip such as cracks is decreased and the semiconductor chip can be cutthinner than a usual case.

Further, since the inter-substrate connecting bumps are temporarily madeto collapse after they are previously applied to the inter-substrateconnecting electrodes, and then cut, the inter-substrate connectingbumps do not slip off from the substrate due to a cutting operation, theconnected states of the inter-substrate connecting bumps and theinter-substrate connecting electrodes are not unstable and theconnecting end faces of prescribed areas can be ensured. Thus, when aplurality of semiconductor devices are layered, the semiconductors canbe respectively easily connected together.

Still further, since the inter-substrate connecting bumps are applied tothe inter-substrate connecting electrodes before the semiconductor chipis mounted on the substrate, there is no possibility that a connectingmaterial used for connecting the semiconductor chip to the wiringpattern on the substrate flows out to the inter-substrate connectingelectrodes to prevent the connection between the inter-substrateconnecting electrodes and the inter-substrate connecting bumps or theconnection between the substrates. Therefore, the inter-substrateconnecting electrodes can be provided at positions near an area wherethe semiconductor chip is mounted and the semiconductor can be madecompact and, especially, a planar configuration can be made compact.

Another method for method for manufacturing a layered semiconductordevice comprises the steps of: forming inter-substrate connecting bumpson one of a front surface or both of front and back surfaces ofinter-substrate connecting electrodes formed on both the front and backsurfaces of a substrate, connected by through holes and connected to awiring pattern so as to be higher than required height; making theinter-substrate connecting bumps to collapse in the direction of thethickness of the substrate to have the height near the required height;connecting electrodes of a semiconductor chip to the wiring patternformed on the substrate and mounting the electrodes of the semiconductorchip on the front surface or both the front and back surfaces of thesubstrate and securing the semiconductor chip to the substrate by apolymer material located so as to surround parts between the substrateand the semiconductor chip and the side surfaces of the semiconductorchip; cutting flat the surfaces of the semiconductor chip and theinter-substrate connecting bumps opposite to the substrate to have thespace of a prescribed thickness between the cut flat surfaces of thesemiconductor chip and the inter-substrate connecting bumps and thesubstrate and to obtain each semiconductor device; layering a pluralityof semiconductor devices thus obtained; and connecting theinter-substrate connecting bumps of the respective semiconductor devicestogether or connecting the inter-substrate connecting bumps to theinter-substrate connecting electrodes.

In another method for manufacturing a layered semiconductor deviceaccording to the present invention, the plural semiconductor deviceseach of which has a semiconductor chip cut extremely thinner than ausual semiconductor chip can be layered and a compact, and especiallythin layered semiconductor device with high integration can bemanufactured. Further, the semiconductor devices can be respectivelyconnected together with high accuracy.

Still another objects of the present invention and specific advantagesobtained by the present invention will be more apparent frombelow-describe embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 3 are sectional views showing one example of a method formanufacturing a conventional semiconductor device and a layeredsemiconductor device. FIG. 1 shows a mounting step of a semiconductorchip, FIG. 2 shows a solder bump forming step and FIG. 3 shows a layeredsemiconductor device.

FIG. 4 is a schematic sectional view showing a first embodiment of asemiconductor device according to the present invention.

FIG. 5 is a schematic sectional view showing a second embodiment of thesemiconductor device according to the present invention.

FIG. 6 is a schematic sectional view showing a first embodiment of alayered semiconductor device according to the present invention.

FIG. 7 is a schematic sectional view showing a second embodiment of thelayered semiconductor device according to the present invention.

FIGS. 8 to 12 are sectional views showing a first embodiment of a methodfor manufacturing a semiconductor device according to the presentinvention. FIG. 8 shows a step of forming inter-substrate connectingbumps, FIG. 9 shows a step of forming stud bumps on electrodes for achip, FIG. 10 shows a mounting step of a semiconductor chip, FIG. 11shows an encapsulating step by an encapsulating resin and FIG. 12 showsa grinding step.

FIGS. 13 to 20 are sectional views showing a second embodiment of amethod for manufacturing a semiconductor device according to the presentinvention. FIG. 13 shows a step of forming inter-substrate connectingbumps, FIG. 14 shows a step of forming stud bumps on electrodes for achip on one surface of a substrate, FIG. 15 shows a step of mounting asemiconductor chip on one surface of the substrate, FIG. 16 shows anencapsulating step on one surface of the substrate by an encapsulatingresin, FIG. 17 shows a step of forming stud bumps on electrodes for achip on the other surface of the substrate, FIG. 18 shows a state inwhich an encapsulating step of the other surface of the substrate iscompleted, FIG. 19 shows a cutting step of one surface of the substrateand FIG. 20 shows a cutting step of the other surface of the substrate.

FIG. 21 is a sectional view showing a third embodiment of asemiconductor device according to the present invention and FIG. 22 is aside view of the above-described semiconductor device.

FIG. 23 is a sectional view showing a third embodiment of a layeredsemiconductor device and FIG. 24 is a substantial side view of theabove-described layered semiconductor device.

FIG. 25 is a sectional view showing a fourth embodiment of asemiconductor device according to the present invention.

FIGS. 26 to 31 are sectional views showing in order of steps a methodfor manufacturing the semiconductor device according to the fourthembodiment of the present invention. FIG. 26 shows a step of applyinginter-substrate connecting bumps to a substrate, FIG. 27 shows a step ofmaking the inter-substrate connecting bumps to collapse so as to have aprescribed thickness, FIG. 28 shows a step of mounting electrodes onsemiconductor chips, FIG. 29 shows a step of mounting the semiconductorchips on the substrate, FIG. 30 shows a step of mounting thesemiconductor chips on the substrate to achieve a conduction and FIG. 31shows a grinding step.

FIG. 32 is a sectional view showing a semiconductor memory device towhich the fourth embodiment of the layered semiconductor deviceaccording to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, embodiments of a semiconductor device, a layered semiconductordevice, methods for manufacturing the semiconductor device and thelayered semiconductor device will be described by referring thedrawings.

Firstly, a first embodiment of the semiconductor device according to thepresent invention will be described by referring to FIG. 4. Asemiconductor device shown in FIG. 4 has a substrate 2. On one surfaceside 2 a of the substrate 2, a semiconductor chip 3 is mounted andinter-substrate connecting bumps 4 are provided. The semiconductor chip3 and the inter-substrate connecting bumps 4 mounted on the substrate 2are encapsulated by an encapsulating resin 5. The surfaces of thesemiconductor chip 3, the inter-substrate connecting bumps 4 and theencapsulating resin 5 opposite to the substrate 2, that is, surfacesfacing the front surface side of the semiconductor 1 in FIG. 4 serve ascut flat surfaces 3 a, 4 a and 5 a, respectively. The cut flat surfaces3 a, 4 a and 5 a are all cut so as to be located in the same plane.

In the semiconductor device 1 shown in FIG. 4, the thickness D₁ of thesubstrate 2 ranges from 100 m to 150 m. The thickness D₂ from onesurface 2 a of the substrate 2 to the respective cut flat surfaces 3 a,4 a and 5 a is about 50 m and an entire thickness D₃ ranges from about150 m to 200 m.

Subsequently, a second embodiment of the semiconductor device accordingto the present invention will be described by referring to FIG. 5. In asemiconductor device 1A shown in FIG. 5, a semiconductor chip 3 ismounted on the other surface side 2 b of a substrate 2 as well as onesurface side 2 a and inter-substrate connecting bumps 4 are provided.That is, in the semiconductor device 1A, the semiconductor chips 3 aremounted and the inter-substrate connecting bumps 4 are provided on boththe surfaces of the substrate 2. Also in this semiconductor device 1A,the semiconductor chip 3 and the inter-substrate connecting bumps 4mounted on the other surface side 2 b of the substrate 2 areencapsulated by an encapsulating resin 5 and the surfaces of thesemiconductor chip 3, the inter-substrate connecting bumps 4 and theencapsulating resin 5 facing surface sides are all cut flat surfaces 3a, 4 a and 5 a, respectively so as to be located in the same plane.

In the semiconductor device 1A shown in FIG. 5, the thickness D₁ of thesubstrate 2 ranges from 100 m to 150 m. The thickness D₂ from onesurface 2 a of the substrate 2 to the respective cut flat surfaces 3 a,4 a and 5 a is about 50 m, the thickness D₄ from the other surface 2 bof the substrate 2 to the respective cut flat surfaces 3 a, 4 a and 5 ais about 50 m and an entire thickness D₅ ranges from about 150 m to 200m.

Now, a first embodiment of a layered semiconductor device according tothe present invention will be described by referring to FIG. 6.

The layered semiconductor device 10 according to the present inventionshown in FIG. 6 is formed by layering the four semiconductor devices 1shown in FIG. 4.

In the layered semiconductor device 10, for instance, solder is appliedto the cut flat surfaces 4 a of the inter-substrate connecting bumps 4of the semiconductor device 1 located in a first layer, lowerinter-substrate connecting electrodes 8 of the semiconductor device 1forming a second layer are superposed on the applied solder, and thesemiconductor device 1 forming a third layer and the semiconductordevice 1 forming a fourth layer are sequentially superposed thereon inthe same manner. Then, the solder applied to parts between thesemiconductor devices 1 is melted by reflow soldering, so that theinter-substrate connecting electrodes 8 are electrically connectedtogether through the inter-substrate connecting bumps 4 and the mutuallylayered semiconductor devices of a layered semiconductor device 10 areelectrically and mechanically connected together. A method forconnecting the semiconductors 1 respectively forming layers is notlimited to a soldering method, and various kinds of connecting methodssuch as connections using ACF, conductive paste or Au bumps may beemployed.

When the inter-substrate connecting bumps 4 are solder bumps, flux isapplied to the cut flat surfaces 4 a thereof and the lowerinter-substrate connecting electrodes 8 of the semiconductor devices 1of upper layers are superposed thereon, so that a plurality ofsemiconductor devices 1 can be layered only by reflow soldering. Sincethe encapsulating resin 5 surrounds the peripheries of the cut flatsurfaces 4 a of the exposed solder bumps 4, the encapsulating resin 5performs a function the same as that of a solder resist. Accordingly,narrow pitches to be extremely hardly mounted can be mounted. Forinstance, when the remaining maximum thickness of the semiconductor chip3 after it is ground is 0.1 mm, the semiconductor chip 3 can meet thesolder bumps 4 with space therebetween of 0.5 mm or more, andaccordingly, a high density mounting can be achieved.

In the layered semiconductor device 10 shown in FIG. 6, when a flashmemory chip of, for instance, 64 megabytes is employed for thesemiconductor chip 3, a memory module of 256 megabytes in which fourflash memories are contained within the thickness of 0.7 mm can beformed. The layered semiconductor device 10 constituted as the memorymodule can be mounted on a circuit board of an electronic device by amethod such as a soldering method to be used as a built-in memory, oraccommodated in a prescribed casing to be formed as a removable memorydevice.

In the layered semiconductor device 10 shown in FIG. 6, the foursemiconductor devices 1 each of which has the semiconductor chip 3mounted on only one or the other surface are layered, however, thenumber of the layered semiconductors is not limited four, and four orsmaller or four or larger number may be suitably selected as required.

On the substrate 2 of each semiconductor device 1 which is layered toform the layered semiconductor device 10, the inter-substrate connectingelectrodes 7 and 8 having the same number are respectively formed on thesame positions to share the substrate 2. When an identification symbolID is required to identify each semiconductor device 1 to be layered,the connecting relation between the respective semiconductor devices 1is specified by controlling to which inter-substrate connectingelectrodes 7 of the substrate 2, the inter-substrate connecting bumps 4are applied and to which inter-substrate connecting electrodes 7, theinter-substrate connecting bumps 4 are not applied, so that theidentification symbol ID peculiar to each semiconductor device 1 can begiven thereto. In this case, the inter-substrate connecting electrodes 7in which the inter-substrate connecting bumps 4 are not provided arecovered with the encapsulating resin 5. Since this encapsulating resin 5serves as the resist, an erroneous connection due to swelling out solderis prevented. Therefore, after the flux is applied to the exposed solderbumps 4, the prescribed number of semiconductor devices 1 are layered,and then, the preferable electrical and mechanical connection betweenthe respective semiconductor devices 1 is realized by reflow soldering.

Now, a second embodiment of a layered semiconductor device according tothe present invention is shown in FIG. 7. In the layered semiconductordevice 10A shown in FIG. 7, are layered two both-surface typesemiconductor devices each of which has a semiconductor chip 3 andinter-substrate connecting bumps 4 mounted on the other surface side 2 bof a substrate 2 as well as one surface side 2 a of the substrate 2.

In the layered semiconductor device 10A shown in FIG. 7, inter-substrateconnecting bumps 4 provided on upper inter-substrate connectingelectrodes 7 of the semiconductor device 1A located in a lower layerside are connected to inter-substrate connecting bumps 4 provided onlower inter-substrate connecting electrodes 8 of the semiconductordevice 1A located in an upper layer side.

In the layered semiconductor device 10A, when a flash memory chip of,for instance, 64 megabytes is used as the semiconductor chip 3 providedin each semiconductor device 1A, a memory module of 256 megabytes inwhich four flash memory chips are contained within the thickness of 0.5mm can be formed. Further, when four semiconductor devices 1A arelayered, a memory module of 512 megabytes in which eight flash memorychips are contained within the thickness of 1 mm can be formed.

The layered semiconductor device 10A constituted as the memory moduleshown in FIG. 7 may be mounted on a circuit board of an electronicdevice by a method such as a soldering method like the above-describedlayered semiconductor device 10 to be used as a built-in memory, or maybe accommodated in a prescribed casing to be constituted as a removablememory device.

Now, a method for manufacturing the semiconductor device 1 shown in FIG.4 will be described below.

A substrate 2 forming the semiconductor device 1 is an interposedsubstrate with the entire thickness of about 100 m including a corematerial with the thickness of, for instance, about 50 m having a singleside pattern of about 25 m on one surface side. In a semiconductor chipmounting area, electrodes 6 for a chip for connecting electrodes notshown in the drawing of a semiconductor chip 3, for instance, a siliconchip to a wiring pattern not shown in the drawing are provided.Electrodes 7 and 8 for connecting the electrodes 6 for the chip toexternal parts are provided outside the semiconductor electrode mountingarea. Since the electrodes 7 and 8 for connecting the electrodes 6 forthe chip to the external parts are mainly used for connectinginter-spaces of the substrate 2, they are explained by using the name of“inter-substrate connecting electrodes” in the following description.The inter-substrate connecting electrodes 7 and 8 provided on one andthe other surfaces of the substrate 2, that is, on both the front andback surfaces are electrically connected by through holes 9 bored in thesubstrate 2 as shown in FIG. 8. The substrate 2 shown in FIG. 8 shows anarea corresponding to one semiconductor device 1 and peripheral partsthereof. However, actually, many areas are formed integrally and theyare divided into individual semiconductor devices 1 after all processesare completed. As shown in FIG. 4, in the substrate 2 having thesemiconductor chip 3 mounted on only one surface, the pattern andelectrodes for the chip are formed on only one surface 2 a and only theinter-substrate connecting electrodes 8 are formed on the other surface2 b.

In order to manufacture the semiconductor device 1 shown in FIG. 4, theinter-substrate connecting bumps 4 are firstly formed on theinter-substrate connecting electrodes 7 on a surface of the substrate 2on which the semiconductor chip 3 is mounted, as shown in FIG. 8. Forinstance, when the inter-substrate connecting bumps 4 are solder bumps,solder is applied to the inter-substrate connecting electrodes 7 to formthe bumps by a reflow soldering method. The inter-substrate connectingbumps 4 are formed to be higher than a finally required height.

Then, as shown in FIG. 9, stud bumps 11 are formed on the electrodes 6for the chip provided on one surface side 2 a of the substrate 2. Thestud bumps 11 are, for example, Au stud bumps, and formed by employing astud bump bonding device or a wire bonding device.

Then, as shown in FIG. 10, the semiconductor chip 3 is mounted on theone surface side 2 a of the substrate 2. That is, the semiconductor chip3, for instance, the silicon chip is mounted on the semiconductor chipmounting area while its face directed downward, electrodes on thesemiconductor chip 3 not shown in the drawing are connected to the studbumps 11, a reinforcing resin 12 is supplied to a part between thesemiconductor chip 3 and the substrate 2 and cured. The thickness of thesemiconductor chip 3 may be larger than a finally required thickness.For instance, even when it is desired to finally obtain the thickness ofthe semiconductor chip 3 of 50 m, the semiconductor chip having thethickness of 200 m or larger can be used.

The electrodes on the semiconductor chip 3 are connected to the studbumps 11 by using, for instance, a ultrasonic bonding device andapplying a ultrasonic wave from the back side of the semiconductor chipmounting surface 2 a of the substrate 2. The electrodes of thesemiconductor chip 3 may be connected to the electrodes 6 for the chipby other flip chip connecting methods except the ultrasonic bondingmethod such as ACF, C4, ACP, etc.

When the connection of the electrodes of the semiconductor chip 3 to theelectrodes 6 for the chip is completed, the reinforcing resin 12 issupplied to an interface between the semiconductor chip 3 and thesubstrate 2 and cured. As the reinforcing resin 12, a suitable resinsuch as a thermosetting resin or a UV curing resin may be employed.Before the electrodes of the semiconductor chip 3 are connected to theelectrodes 6 for the chip, the reinforcing resin 12 may be previouslyapplied to the interface to spread and cure the reinforcing resin 12 inthe interface simultaneously with the ultrasonic bonding.

After that, as shown in FIG. 11, an encapsulating resin 5 is supplied tothe substrate 2 so as to bury the semiconductor chip 3 and theinter-substrate connecting bumps 4 to cure the encapsulating resin 5. Atthis time, the lower surface of the substrate 2, that is, a surface 2 bopposite to the surface 2 a on which the semiconductor chip 3 is mountedis parallel to the upper surface 5 a of the encapsulating resin 5.Therefore, is desirably used a device such as a transfer mold device inwhich the other surface 2 b of the substrate 2 and the upper surface 5 aof the encapsulating resin 5 are fixed by a mold.

Then, the semiconductor chip 3 and the inter-substrate connecting bumps4 and the encapsulating resin 5 are fixed by a surface grinder by usingthe exposed surface of the substrate 2, that is, the other surface 2 bas a reference to grind the upper surface 5 a of the encapsulating resin5 located at the opposite side to the reference surface. Thus, since thesemiconductor chip 3 and the inter-substrate connecting bumps 4 areexposed, the semiconductor chip 3 and the inter-substrate connectingbumps 4 are further ground together with the encapsulating resin 5 untila desired thickness, for instance, the height from the mounting surface2 a of the substrate 2 to the semiconductor chip 3 reaches 50 m (seeFIG. 12).

Then, each part having one semiconductor chip 3 is separated from otherparts to form individual pieces. Thus, the semiconductor device 1 asshown in FIG. 4 is formed in which one semiconductor chip 3 is providedin the thickness of 150 m.

Now, a method for manufacturing the layered semiconductor device 10Ashown in FIG. 7 will be described below.

In the layered semiconductor device 10A shown in FIG. 7, is used asubstrate 2 having patterns and electrodes 6 for chips provided on bothsurfaces. In the layered semiconductor device 10A, as shown in FIG. 13,inter-substrate connecting bumps 4 and 4 are formed on inter-substrateconnecting electrodes 7 and 8 respectively provided on both the surfacesof the substrate 2 on which the semiconductor chips 3 are mounted. Thesesolder bumps 4 and 4 are formed, for instance, by applying solder to theinter-substrate connecting electrodes 7 and 8 and then performing areflow soldering method. The inter-substrate connecting bumps 4 areformed so as to be higher than a finally required height.

Subsequently, as shown in FIG. 14, stud bumps 11 are formed on theelectrodes 6 for the chip provided in one surface side 2 a of thesubstrate 2. The stud bumps 11 are, for instance, Au stud bumps andformed by employing a stud bump bonding device or a wire bonding device.

Then, the stud bumps 11 are connected to the electrodes of thesemiconductor chip 3. As shown in FIG. 15, a reinforcing resin 12 isallowed to enter an interface between the substrate 2 and thesemiconductor chip 3 and cured to mount the semiconductor chip 3. Afterthat, as shown in FIG. 16, the semiconductor chip 3 and theinter-substrate connecting bumps 4 on the one surface 2 a of thesubstrate 2 are encapsulated by an encapsulating resin 5.

Then, as shown in FIG. 17, stud bumps 11 are likewise formed onelectrodes 6 for a chip on the other surface 2 b of the substrate 2 anda mounting step of the semiconductor chip 3 and an encapsulating step bythe encapsulating resin 5 are carried out as shown in FIG. 18 after thesame steps are performed on the one surface 2 a.

Subsequently, as shown in FIG. 19, a grinding operation is carried outon the one surface 2 a of the substrate 2, and then, the grindingoperation is also carried out on the other surface 2 b of the substrate2 as shown in FIG. 20. For instance, when one and the other surfaces 2 aand 2 b of the substrate 2 are respectively ground until a desiredthickness, for instance, the height H₁ of the semiconductor chip 3 fromeach of surfaces 2 a and 2 b of the substrate 2 on which thesemiconductor chip 3 is mounted reaches 50 m, two semiconductor chips 3and 3 can be accommodated within a range of an entire thickness D₆ of200 m by using the substrate 2 whose thickness D₁ ranges from 100 m to150 m.

A part in which each semiconductor chip 3 is provided in each ofsurfaces 2 a and 2 b of the substrate 2 is separated from other parts toform individual parts. Thus, is formed the semiconductor device 1A asshown in FIG. 5 in which two semiconductor chips 3 are provided within arange of the thickness D₆ of 200 m.

In the semiconductor device 1 and the semiconductor device 1A accordingto the present invention, after the semiconductor chip 3 mounted on thesubstrate 2 with its face directed downward is encapsulated by theencapsulating resin 5, the semiconductor chip 3 is cut together with theencapsulating resin 5. Accordingly, load applied upon cutting isdistributed to the encapsulating resin 5 so that the load exerted on thesemiconductor chip 3 becomes extremely small, the damage of thesemiconductor chip 3 such as cracks upon cutting can be assuredlyprevented, the semiconductor chip 3 can be cut to be thinner and themounting density of the semiconductor chip 3 can be improved within aprescribed thickness.

Since the inter-substrate connecting bumps 4 are formed on theinter-substrate connecting electrodes 7 and/or 8 for electricallyconnecting an inter-space of the substrate 2 or the substrate 2 toexternal connecting parts before the semiconductor chip 3 is mounted onthe substrate 2, even when a connecting material flows out to theinter-substrate connecting electrodes to come into contact with theinter-substrate connecting bumps 4 or bury the inter-substrateconnecting bumps 4 in accordance with the flip chip bonding uponmounting the semiconductor chip 3, the connecting material is removed bya subsequent cutting step. Therefore, the space between the mountingarea of the semiconductor chip 3 and the inter-substrate connectingbumps 4 and the space between the inter-substrate connecting bumps 4 canbe decreased. Consequently, the planar forms of the semiconductor device1 and the semiconductor device 1A can be made compact.

Now, a third embodiment of a semiconductor device according to thepresent invention will be described by referring to FIGS. 21 and 22.

In the semiconductor device 1B according to the third embodiment shownin FIGS. 21 and 22, through holes 9 and inter-substrate connecting bumps4 provided in the semiconductor device 1A according to the secondembodiment are exposed to the side surfaces of the substrate 2. That is,the through holes 9 and the inter-substrate connecting bumps 4 areformed so as to be visually seen from the side parts of thesemiconductor device 1B in the direction of an arrow mark A in FIG. 21.When a part having one semiconductor chip 3 on each of both surfaces ofthe substrate 2 is formed as an individual piece in the steps ofmanufacturing the semiconductor device 1A shown in FIG. 5, theindividual piece is formed by cutting parts where the through holes 9and the inter-substrate connecting bumps 4 are located. When theindividual piece is formed, parts outside the parts where the throughholes 9 and the inter-substrate connecting bumps 4 are located may becut, and then, the parts where the though holes 9 and theinter-substrate connecting bumps 4 are located may be cut. These throughholes 9 and the inter-substrate connecting bumps 4 may be exposed to theside surfaces.

Now, referring to FIGS. 23 and 24, a third embodiment of a layeredsemiconductor device according to the present invention will bedescribed below.

The layered semiconductor device 10B shown in FIGS. 23 and 24 is formedby layering a plurality of semiconductor devices 1B shown in FIGS. 21and 22 in which the through holes 9 and the inter-substrate connectingbumps 4 are exposed to the side surface of the substrate 2.

As described above, when the layered semiconductor device 10B ismanufactured by layering a plurality of semiconductor devices 1B eachhaving the through holes 9 and the inter-substrate connecting bumps 4exposed to the side surfaces of the substrate 2, the connected states ofthe inter-substrate connecting bumps 4 of the semiconductor devices 1Brespectively layered vertically can be visually recognized from the sideparts and the imperfect connections between the semiconductor devices 1Bcan be assuredly decreased. Further, when the inter-substrate connectingbumps 4 are connected together by heating, for instance, where theinter-substrate connecting bumps 4 are formed by solder, the connectingmaterial such as flux or the inter-substrate connecting bumps 4 cannotbe directly heated in the semiconductor device 1 according to the firstembodiment and the semiconductor device 1A according to the secondembodiment. However, since the inter-substrate connecting bumps 4 areexposed to the side surfaces of the substrate 2 in the layeredsemiconductor device 10B according to the third embodiment, theconnecting material or the inter-substrate connecting bumps 4 can bedirectly heated from the side surfaces by using, for instance, asoldering iron, etc. to connect the inter-substrate connecting bumps 4together.

Now, a fourth embodiment of a semiconductor device will be described byreferring to FIG. 25.

A semiconductor device 1C shown in FIG. 25 has semiconductor chips 3 and3 respectively mounted on both surfaces of one surface 2 a and the othersurface 2 b of a substrate 2. Surfaces 3 a and 3 a opposite to thesurfaces of the semiconductor chips 3 and 3 opposed to the substrate 2are cut to be thin. The semiconductor chips 3 and 3 are connected to thesubstrate 2 by polymer materials 13 and 13. The polymer materials 13 and13 adhere round to the four side surfaces of the semiconductor chips 3and 3. In FIG. 25, the polymer materials 13 adhere to the two opposedsurfaces of the semiconductor chips 3.

Further, inter-substrate connecting bumps 4 are respectively provided oninter-substrate connecting electrodes 7 provided on one surface 2 a ofthe substrate 2 and inter-substrate connecting electrodes 8 provided onthe other surface 2 b of the substrate 2. After these inter-substrateconnecting bumps 4 are respectively formed on the inter-substrateconnecting electrodes 7 and 8, they are made to collapse so as to haveprescribed thickness. Further, the inter-substrate connecting bumps 4are formed so that they have flat surfaces 4 a cut so as to be locatedin the same plane as that of the cut flat surfaces 3 a of thesemiconductor chips 3.

In the semiconductor device 1C formed as shown in FIG. 25, since thesemiconductor chips 3 and 3 respectively provided on both the surfaces 2a and 2 b of the substrate 2 are fixed to the substrate 2 by the polymermaterials 13 and 13 rounding the side surfaces thereof, load exerted onthe semiconductor chips 3 is distributed when the semiconductor chips 3are ground to desired thickness to suppress the load applied to thesemiconductor chips 3 and 3 upon grinding and more decrease thethickness while the semiconductor chips 3 and 3 are assuredly protected.

The semiconductor device 1C shown in FIG. 25 is different from thesemiconductor device 1, the semiconductor device 1A and thesemiconductor device 1B. In the semiconductor device 1C, since only theperiphery of the semiconductor chip 3 is covered with the encapsulatingresin and the entire part of the semiconductor chip 3 is not buried inthe encapsulating resin, the encapsulating resin does not need to beground when the semiconductor chip is ground to a prescribed thickness,so that a grinding operation can be efficiently carried out and theexhaustion of a grinder can be reduced.

In the semiconductor device 1C shown in FIG. 25, in order to fix thesemiconductor chip 3 to the substrate 2 and connect the electrodes ofthe semiconductor chip 3 to electrodes 6 for the chip on the substrate2, for example, an anisotropic conductive material can be employed.Since the anisotropic conductive material is employed tothermocompression-bond the anisotropic conductive material providedbetween the semiconductor chip 3 and the substrate 2, the semiconductorchip 3 can be fixed to the substrate 2 and the electrodes of thesemiconductor chip 3 can be conducted to the electrodes 6 for the chipon the substrate 2 at the same time. Thus, a workability is improved.The anisotropic conductive material may be provided in the form of anACP (anisotropic conductive paste). When the anisotropic conductivematerial is supplied in the form of an ACF (anisotropic conductivefilm), it is easily handled so that the workability of a method formanufacturing the semiconductor device 1C can be improved. Thesemiconductor chip 3 is positioned on the substrate 2 and stuck theretoby using the ACF and the semiconductor chip 3 isthermocompression-bonded under this state to electrically connect theelectrodes of the semiconductor chip 3 to the electrodes 6 for the chipon the substrate 2 and fix the semiconductor chip 3 to the substrate 2by the polymer material 13 as a binder of the ACF. As the polymermaterial 13 for fixing the semiconductor chip 3 to the substrate 2, theanisotropic conductive material does not need to be necessarily used.

Further, in the semiconductor device 1C shown in FIG. 25, after theinter-substrate connecting bumps 4 are provided on the substrate 2, theinter-substrate connecting bumps 4 are made to collapse to positionsnear the height obtained by grinding, and then, ground to a prescribedheight. Since the inter-substrate connecting bumps 4 formed on thesubstrate 2 come into firmly and tightly contact with the substrate 2and the inter-substrate connecting electrodes 7 and 8 formed on thesubstrate 2 by the collapsing step, the inter-substrate connecting bumps4 can be certainly prevented from slipping off from the substrate 2 dueto a grinding operating and the reliability of the obtainedsemiconductor device 1C is improved.

Although, in the semiconductor device 1C shown in FIG. 25, thesemiconductor chips 3 are respectively mounted on the surfaces 2 a and 2b of the substrate 2, it is understood that the present invention may beapplied to a semiconductor device in which the semiconductor chip 3 ismounted on only one surface 2 a or a surface 2 b of the substrate 2.

Now, a method for manufacturing the semiconductor device 1C according tothe fourth embodiment will be described below by referring to FIGS. 26to 31.

In order to manufacture the semiconductor device 1C, as shown in FIG.26, is prepared a substrate 2 having electrodes 6 and 6 for chips andinter-substrate connecting electrodes 7 and 8 respectively formed on onesurface 2 a and the other surface 2 b. In the substrate 2, are formedconductor patterns not shown in the drawing by which the electrodes 6and 6 for the chips and the inter-substrate connecting electrodes 7 and8 respectively formed on one surface 2 a and the other surface 2 b areelectrically connected together. Further, through holes 9 are formed toelectrically connect the inter-substrate connecting electrodes 7 and 8respectively formed on the one surface 2 a and the other surface 2 b. Asshown in FIG. 26, inter-substrate connecting bumps 4 are formed on theinter-substrate connecting electrodes 7 and 8 respectively formed on thesurfaces 2 a and 2 b of the substrate 2. The inter-substrate connectingbumps 4 are formed in such a manner that the height t₁ of the bumps isslightly larger than the height T of the semiconductor chip 3 after agrinding operation (see FIG. 25).

When the inter-substrate connecting bumps 4 formed on theinter-substrate connecting electrodes 7 and 8 are solder bumps, solderis initially applied to the one surface 2 a of the substrate 2 by, forinstance, a screen printing method and a reflow soldering process isperformed. Then, solder is likewise applied to the other surface 2 b ofthe substrate 2 by the screen printing method and the reflow solderingprocess is performed to form the solder bumps. In such a manner, thedome shaped solder bumps 4 are respectively formed on both the surfacesof one surface 2 a and the other surface 2 b of the substrate 2.

The inter-substrate connecting bumps 4 respectively formed on thesurfaces 2 a and 2 b of the substrate 2 are made to collapse at the sametime by a press molding so as to have a presecribed height t as shown inFIG. 27. The prescribed height t is a slightly larger than the height ofthe semiconductor chip 3 after the semiconductor chip 3 is ground. Whenthe inter-substrate connecting bumps 4 are formed by the solder bumps,an unevenness in the amount of supply of solder cannot be avoided evenin the screen printing method by which the solder is relativelyuniformly supplied. The unevenness of the supply of solder appears as anunevenness in height of supplied solder, however, the collapsing step iscarried out so that the heights t of the inter-substrate connectingbumps 4 are accurately made uniform. The accuracy of height of theinter-substrate connecting bumps 4 before the grinding operation isimproved as described above, and accordingly, pressure applied in thedirection of the thickness of the substrate 2 upon grinding can beequally received by the inter-substrate connecting bumps 4 respectivelylocated at opposite sides and the deflection of the substrate 2 upongrinding can be prevented.

As shown in FIG. 28, on the electrodes of the semiconductor chips 3 notshown in the drawing, stud bumps 11 are formed. The stud bumps 11 are,for instance, Au stud bumps and formed by using a stud bonding device ora wire bonding device.

Then, as shown in FIG. 29, the semiconductor chips 3 having the studbumps 11 formed are mounted on one and the other surfaces 2 a and 2 b ofthe substrate 2 while they are positioned thereon. That is, thesemiconductor chips 3 are arranged respectively on the surfaces 2 a and2 b of the substrate 2 in such a manner that the surfaces having thestud bumps 11 formed are opposed to the surfaces 2 a and 2 b of thesubstrate 2 to locate the stud bumps 11 on the electrodes 6 for thechips.

The semiconductor chips 3 disposed on the substrate 2 are respectivelystuck to the surfaces 2 a and 2 b of the substrate 2 by, for instance,ACFs (anisotropic conductive films) 14. The ACF is formed by dispersingconductive particles in an adhesive (binder) composed of a polymermaterial to have a film type material and coating a separator therewith.The ACFs are interposed between the semiconductor chips 3 and thesubstrate 2 by peeling off the separators not shown in the drawing tostick the semiconductor chips 3 to the substrate 2. When thesemiconductor chips 3 and 3 are connected to the substrate 2 throughanisotropic conductive materials, a paste type anisotropic conductivematerial (ACP) may be also employed. When the anisotropic conductivematerial is supplied in the form of ACP, an exclusive dispenser isrequired so that the device becomes large and it is troublesome tohandle it. However, since the above-described ACF is used, the devicecan be easily handled and the large device is not required.

The substrate 2 having the semiconductor chips 3 stuck to the respectivesurfaces 2 a and 2 b through the ACFs is thermocompression-bonded. Thatis, the semiconductor chips 3 are thermocompression-bonded in thedirections shown by arrow marks B in FIG. 30 so as to press thesemiconductor chips 3 to the substrate 2 under slightly hightemperature. The semiconductor chips 3 are thermocompression-bonded, sothat the electrodes provided in the chips 3 are electrically conductedto the electrodes 6 for the chips in the substrate 2 opposed thereto bythe stud bumps 11 and the conductive particles of the anisotropicconductive materials 14 and parts except the opposed electrodes areinsulated. At the same time, the binder softened by heating flows roundthe side surfaces of the semiconductor chips 3 and the side surfaces arecoated with the binder. As a result, the surfaces of the semiconductorchips 3 opposed to the substrate 2 and the side surfaces with the binderso that the semiconductor chips 3 are fixed to the substrate 2.

In the example shown in FIGS. 29 and 30, although the semiconductorchips 3 are mechanically fixed to the substrate 2 and electricallyconnected to the substrate 2 at the same time by employing theanisotropic conductive material, the present invention is not limitedthereto, and other method may be used, for instance, after thesemiconductor chips 3 are electrically connected to the substrate 2, thepolymer material may be supplied to the parts between the semiconductorchips 3 and the substrate 2 to mechanically fix the semiconductor chips3 to the substrate 2.

As described above, the semiconductor chips 3 mounted respectively onthe surfaces 2 a and 2 b of the substrate 2 and the inter-substrateconnecting bumps 4 formed respectively on the surfaces 2 a and 2 b ofthe substrate 2 are ground so as to have prescribed thickness from eachof the surfaces 2 a and 2 b of the substrate 2. In the semiconductordevice 1C according to the present invention, since the semiconductorchips 3 and the inter-substrate connecting bumps 4 are respectivelyground so as to have desired thickness, the semiconductor device 1Cshown in FIG. 31 is considered to be a completed semiconductor devicemounted on an electronic device. The semiconductor device 1C shown inFIG. 31 is formed to have its thickness DT of about 0.28 mm.

The thickness of the semiconductor chip 3 after it is ground and thethickness BT of the substrate 2 are desirably set to substantially equalthickness. For instance, in the substrate 2, the thickness of a basematerial is set to 0.055 to 0.065 mm, the thickness of the conductorpattern including the electrodes 6, 7 and 8 is set within a range of0.011 to 0.015 mm. The semiconductor chip 3 having the thickness ofabout 0.2 mm before a grinding process upon mounting on the substrate 2is ground to have the thickness of 0.06 to 0.08 mm. The entire thicknessof the semiconductor device 1C is set to about 0.28 mm.

When the semiconductor device having the semiconductor chip 3 mounted ononly one surface of the substrate 2 is manufactured, the above-describedsteps may be respectively carried out on only one surface of thesubstrate 2.

Now, as a fourth embodiment of the present invention, a layeredsemiconductor device 10C formed by layering the four semiconductordevices 1C and a semiconductor memory device 15 using the layeredsemiconductor device 10C are shown in FIG. 32.

The layered semiconductor device 10C shown in FIG. 32 is formed so as tohave its thickness LT of about 1.15 mm. Before the layered semiconductordevice 10C is mounted on a mother board 16, protective substrates 17 and18 are respectively attached to upper and lower surfaces to improve amaneuverability. In the lower protective substrate 18, are formed apattern and through holes not shown in the figure for electricallyconnecting the layered semiconductor device 10C to electrodes not shownon the lower surface of the protective substrate 18. The electrodes onthe lower surface are formed at positions deviating from inter-substrateconnecting electrodes 7 and 8 when viewed vertically in the direction ofthe thickness of the substrate 2.

In the semiconductor devices 1C constructed as shown in FIG. 32, aplurality of solder bumps 19 are provided on electrodes of the motherboard 16 not shown in the figure, and the semiconductor devices 1C areconnected to a circuit on the mother board 16 through these solder bumps19. The mother board 16 on which the layered semiconductor device 10C ismounted is accommodated in a package 20 to form, for instance asemiconductor memory device 15. The electrodes on the lower surface ofthe lower protective substrate 18 are formed at the positions verticallydeviating from the inter-substrate connecting electrodes 7 and 8,because the concentration of stress is avoided at the positions wherethe inter-substrate connecting electrodes 7 and 8 and theinter-substrate connecting bumps 4 are located when pressure is appliedin the direction of thickness of the substrate 2.

Further, a layered semiconductor device in which a plurality ofsemiconductor devices each of which has a semiconductor chip 3 mountedon only a single surface of the substrate 2 are layered may be used tomanufacture a semiconductor memory device the same as the semiconductormemory device 15 shown in FIG. 32.

The form and the structure of each part described in each embodimentshow one specific example when the present invention is embodied, andtherefore, they can be suitably modified without departing the gist ofthe present invention.

INDUSTRIAL APPLICABILITY

As described above, according to the present invention, since thesemiconductor chip attached to the substrate is cut together with theencapsulating resin to have a desired thickness, load upon cutting thesemiconductor chip is distributed to the encapsulating resin withoutconcentrating the load to the semiconductor chip, the damage of thesemiconductor chip such as cracks can be reduced and the semiconductorchip can be assuredly cut to have a thin form. Since the inter-substrateconnecting bumps formed on the inter-substrate connecting electrodesprovided on the substrate are also covered with the encapsulating resin,and then cut together with the encapsulating resin to be exposed, theimperfect connection between the inter-substrate connecting bumps andthe inter-substrate connecting electrodes can be certainly prevented andthe connecting end surfaces of prescribed areas of the bumps are formed.

According to the present invention, the thin semiconductor device havinga storage capacity increased and high reliability can be obtained. Thissemiconductor device is used so that a thin semiconductor memory devicehaving a large capacity and high reliability can be obtained.

1. A method for manufacturing a layered semiconductor device, comprisingthe steps of: forming inter-substrate connecting bumps on one of a frontsurface or both of front and back surfaces of inter-substrate connectingelectrodes formed on both front and back surfaces of a substrate,connected by through holes and connected to a wiring pattern, so as tobe higher than a required height; connecting electrodes of asemiconductor chip to the wiring pattern formed on the substrate andmounting the electrodes of the semiconductor chip on the front surfaceor both the front and back surfaces of the substrate; applying anencapsulating resin to the substrate so as to cover the semiconductorchip and the inter-substrate connecting bumps therewith so as to form anencapsulated unit having a top surface and a plurality of side surfaces;and cutting flat the top surface of the encapsulated unit so as to havea prescribed distance between the substrate and the cut flat surfaces ofthe encapsulating resin, the semiconductor chip and the inter-substrateconnecting bumps and cutting a number of the side surfaces where anumber of through holes and the inter-substrate connecting bumps arelocated to expose the number of through holes and the inter-substrateconnecting bumps on the number of side surfaces so that eachsemiconductor device is formed; layering a plurality of semiconductordevices; and connecting the inter-substrate connecting bumps of therespective semiconductor devices together or the inter-substrateconnecting bumps and the inter-substrate connecting electrodes together.2. A method f or manufacturing a semiconductor device, comprising thesteps of: forming inter-substrate connecting bumps on one of a frontsurface or both of front and back surfaces of inter-substrate connectingelectrodes formed on both front and back surfaces of a substrate,connected by through holes and connected to a wiring pattern, so as tobe higher than a required height and making the inter-substrateconnecting bumps collapse in a direction of the thickness of thesubstrate to have the height near the required height; connectingelectrodes of a semiconductor chip to the wiring pattern formed on thesubstrate and mounting the electrodes of the semiconductor chip on thefront surface or both the front and back surfaces of the substrate;applying a polymer material to only a portion of the semiconductor chipand the substrate so as not to cover the collapsed inter-substrateconnecting bumps, the entire semiconductor chip, and the entiresubstrate; and cutting flat the surfaces of the semiconductor chip andthe inter-substrate connecting bumps opposite to the substrate to have aprescribed distance between the cut flat surfaces of the semiconductorchip and the cut flat surfaces of the inter-substrate connecting bumpsand the substrate.
 3. The method for manufacturing a semiconductordevice according to claim 2, wherein the steps of connecting theelectrodes of the semiconductor chip to the wiring pattern formed on thesubstrate and mounting the electrodes of the semiconductor chip on thefront surface or both the front and back surfaces of the substrate andapplying the polymer material to only a portion of the semiconductorchip and the substrate comprise: mounting the semiconductor chip on thesubstrate by an anisotropic conductive material, and applying pressureand heat to the semiconductor chip so as to press the semiconductor chipto the substrate.
 4. The method for manufacturing a semiconductor deviceaccording to claim 3, wherein the anisotropic conductive material issupplied in the form of a film.
 5. A method for manufacturing a layeredsemiconductor device, comprising the steps of: forming inter-substrateconnecting bumps on one of a front surface or both of front and backsurfaces of inter-substrate connecting electrodes formed on both frontand back surfaces of a substrate, connected by through holes andconnected to a wiring pattern, so as to be higher than a requiredheight; making the inter-substrate connecting bumps collapse in adirection of the thickness of the substrate to have a height near therequired height; connecting electrodes of a semiconductor chip to thewiring pattern formed on the substrate and mounting the electrodes ofthe semiconductor chip on the front surface or both the front and backsurfaces of the substrate; applying a polymer material to only a portionof the semiconductor chip and the substrate so as not to cover thecollapsed inter-substrate connecting bumps, the entire semiconductorchip, and the entire substrate; cutting flat the surfaces of thesemiconductor chip and the inter-substrate connecting bumps opposite tothe substrate to have a prescribed distance between the cut flatsurfaces of the semiconductor chip and the cut flat surfaces of theinter-substrate connecting bumps and the substrate to obtain eachsemiconductor device; layering a plurality of semiconductor devices thusobtained; and connecting the inter-substrate connecting bumps of therespective semiconductor devices together or connecting theinter-substrate connecting bumps to the inter-substrate connectingelectrodes.
 6. A method for manufacturing a layered semiconductor devicehaving a plurality of semiconductor devices in which each semiconductordevice has a substrate with front and back surfaces, a wiring circuit, anumber of through holes arranged within the substrate, and a number ofpairs of electrodes, each pair of electrodes having a first electrodearranged on the front surface of the substrate and a second electrodearranged on the back surface of the substrate, the first and secondelectrodes being electrically connected together by a respective throughhole and being electrically connected to the wiring circuit, said methodcomprising the steps of: forming a connecting bump with a height higherthan a final height on an upper surface of the first electrode of arespective pair of electrodes; connecting electrodes of a semiconductorchip to the wiring circuit and mounting the semiconductor chip on thefront surface of the substrate; applying an encapsulating resin to thefront surface of the substrate so as to cover the semiconductor chip andthe connecting bump so as to form an encapsulated unit having a topsurface and a plurality of side surfaces; and cutting the top surface ofthe encapsulated unit until a distance between the front surface of thesubstrate and each of the cut surface of the encapsulating resin, thecut surface of the semiconductor chip, and the cut surface of theconnecting bump has a predetermined value; cutting a number of the sidesurfaces of the encapsulated unit at positions where a number of thethrough holes and the connecting bump are located such that the numberof through holes and the connecting bump are exposed after cutting so asto form a semiconductor device; arranging a plurality of semiconductordevices on top of each other; and connecting the connecting bump of onesemiconductor device to the second electrode of an adjacentsemiconductor device.
 7. A method for manufacturing a layeredsemiconductor device having a plurality of semiconductor devices inwhich each semiconductor device has a substrate with front and backsurfaces, a wiring circuit, a number of through holes arranged withinthe substrate, and a number of pairs of electrodes, each pair ofelectrodes having a first electrode arranged on the front surface of thesubstrate and a second electrode arranged on the back surface of thesubstrate, the first and second electrodes being electrically connectedtogether by a respective through hole and being electrically connectedto the wiring circuit, said method comprising the steps of: forming afirst connecting bump with a height higher than a final height on anupper surface of the first electrode of a respective pair of electrodes,and forming a second connecting bump with a height higher than the finalheight on an upper surface of the second electrode of the respectivepair of electrodes; connecting electrodes of a first semiconductor chipto the wiring circuit and mounting the first semiconductor chip on thefront surface of the substrate; connecting electrodes of a secondsemiconductor chip to the wiring circuit and mounting the secondsemiconductor chip on the back surface of the substrate; applying anencapsulating resin to the front and back surfaces of the substrate soas to cover the first and second semiconductor chips and the first andsecond connecting bumps so as to form an encapsulated unit having a topsurface, a bottom surface, and a plurality of side surfaces, in whichthe top surface of the encapsulated unit faces the front surface of thesubstrate, and the bottom surface of the encapsulated unit faces theback surface of the substrate; and cutting the top surface of theencapsulated unit until a distance between the front surface of thesubstrate and each of the cut surface of the encapsulating resin on thefront surface of the substrate, the cut surface of the firstsemiconductor chip, and the cut surface of the first connecting bump hasa first predetermined value, and cutting the bottom surface of theencapsulated unit until a distance between the back surface of thesubstrate and each of the cut surface of the encapsulating resin on theback surface of the substrate, the cut surface of the secondsemiconductor chip, and the cut surface of the second connecting bumphas a second predetermined value so as to form a semiconductor device;cutting a number of the side surfaces of the encapsulated unit atpositions where a number of the through holes and the first and secondconnecting bumps are located such that the number of through holes andthe first and second connecting bumps are exposed after cutting so as toform a semiconductor device; arranging a plurality of semiconductordevices on top of each other; and connecting the first connecting bumpof one semiconductor device to the second connecting bump of an adjacentsemiconductor device.
 8. A method for manufacturing a semiconductordevice having a substrate with front and back surfaces, a wiringcircuit, a number of through holes arranged within the substrate, and anumber of pairs of electrodes, each pair of electrodes having a firstelectrode arranged on the front surface of the substrate and a secondelectrode arranged on the back surface of the substrate, the first andsecond electrodes being electrically connected together by a respectivethrough hole and being electrically connected to the wiring circuit,said method comprising the steps of: forming a connecting bump with aheight higher than a final height on an upper surface of the firstelectrode of a respective pair of electrodes; causing the connectingbump to collapse in a direction substantially perpendicular to the frontsurface of the substrate so as to reduce its height to that near thefinal height; connecting electrodes of a semiconductor chip to thewiring circuit; applying a polymer material to only a portion of thesemiconductor chip and the front surface of the substrate so as to mountthe semiconductor chip on the front surface of the substrate and so asnot to cover the connecting bump, the entire semiconductor chip, and theentire front surface of the substrate; and cutting top surfaces of thesemiconductor chip and the connecting bump having the reduced heightuntil a distance between the front surface of the substrate and each ofthe cut surface of the semiconductor chip and the cut surface of theconnecting bump has a predetermined value.
 9. The method according toclaim 8, further comprising the steps of: forming a second connectingbump with a height higher than the final height on an upper surface ofthe second electrode of the respective pair of electrodes; causing thesecond connecting bump to collapse in a direction substantiallyperpendicular to the back surface of the substrate so as to reduce itsheight to that near the final height; connecting electrodes of a secondsemiconductor chip to the wiring circuit; applying the polymer materialto only a portion of the second semiconductor chip and the back surfaceof the substrate so as to mount the second semiconductor chip on theback surface of the substrate and so as not to cover the secondconnecting bump, the entire second semiconductor chip, and the entireback surface of the substrate; and cutting the top surfaces of thesecond semiconductor chip and the second connecting bump having thereduced height until a distance between the back surface of thesubstrate and each of the cut surface of the second semiconductor chipand the cut surface of the second connecting bump has a secondpredetermined value.
 10. The method according to claim 9, wherein thefirst predetermined value is approximately the same as the secondpredetermined value.
 11. The method according to claim 9, wherein thepolymer material is an anisotropic conductive material, and wherein eachapplying step includes applying pressure and heat to the respectivesemiconductor chip.
 12. The method according to claim 11, wherein theanisotropic conductive material has a film-like form.
 13. A method formanufacturing a layered semiconductor device having a plurality ofsemiconductor devices in which each semiconductor device has a substratewith front and back surfaces, a wiring circuit, a number of throughholes arranged within the substrate, and a number of pairs ofelectrodes, each pair of electrodes having a first electrode arranged onthe front surface of the substrate and a second electrode arranged onthe back surface of the substrate, the first and second electrodes beingelectrically connected together by a respective through hole and beingelectrically connected to the wiring circuit, said method comprising thesteps of: forming a connecting bump with a height higher than a finalheight on an upper surface of the first electrode of a respective pairof electrodes; causing the connecting bump to collapse in a directionsubstantially perpendicular to the front surface of the substrate so asto reduce its height to that near the final height; connectingelectrodes of a semiconductor chip to the wiring circuit; applying apolymer material to only a portion of the semiconductor chip and thefront surface of the substrate so as to mount the semiconductor chip onthe front surface of the substrate and so as not to cover the connectingbump, the entire semiconductor chip, and the entire front surface of thesubstrate; and cutting top surfaces of the semiconductor chip and theconnecting bump having the reduced height until a distance between thefront surface of the substrate and each of the cut surface of thesemiconductor chip and the cut surface of the connecting bump has apredetermined value so as to obtain a semiconductor device; arranging aplurality of semiconductor devices on top of each other; and connectingthe connecting bump of one semiconductor device to the second electrodeof an adjacent semiconductor device.
 14. A method for manufacturing alayered semiconductor device having a plurality of semiconductor devicesin which each semiconductor device has a substrate with front and backsurfaces, a wiring circuit, a number of through holes arranged withinthe substrate, and a number of pairs of electrodes, each pair ofelectrodes having a first electrode arranged on the front surface of thesubstrate and a second electrode arranged on the back surface of thesubstrate, the first and second electrodes being electrically connectedtogether by a respective through hole and being electrically connectedto the wiring circuit, said method comprising the steps of: forming afirst connecting bump with a height higher than a final height on anupper surface of the first electrode of a respective pair of electrodes;forming a second connecting bump with a height higher than the finalheight on an upper surface of the second electrode of the respectivepair of electrodes; causing the first and second connecting bumps tocollapse in a direction substantially perpendicular to the front andback surfaces of the substrate so as to reduce the height thereof tothat near the final height; connecting electrodes of a firstsemiconductor chip to the wiring circuit; applying a polymer material toonly a portion of the first semiconductor chip and the front surface ofthe substrate so as to mount the first semiconductor chip on the frontsurface of the substrate and so as not to cover the first connectingbump, the entire first semiconductor chip, and the entire front surfaceof the substrate; connecting electrodes of a second semiconductor chipto the wiring circuit; applying the polymer to only a portion of thesecond semiconductor chip and the back surface of the substrate so as tomount the second semiconductor chip on the back surface of the substrateand so as not to cover the second connecting bump, the entire secondsemiconductor chip, and the entire back surface of the substrate;cutting top surfaces of the first semiconductor chip and the firstconnecting bump having the reduced height until a distance between thefront surface of the substrate and each of the cut surface of the firstsemiconductor chip and the cut surface of the first connecting bump hasa first predetermined value, and cutting top surfaces of the secondsemiconductor chip and the second connecting bump having the reducedheight until a distance between the back surface of the substrate andeach of the cut surface of the second semiconductor chip and the cutsurface of the second connecting bump has a second predetermined valueso as to form a semiconductor device; arranging a plurality ofsemiconductor devices on top of each other; and connecting the firstconnecting bump of one semiconductor device to the second connectingbump of an adjacent semiconductor device.